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sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 available as military specification ? smd 5962-95613 1,2 ? mil std-883 1 features ? ultra low power with 2v data retention (0.2mw max worst case power-down standby) ? fully static, no clocks ? single +5v 10% power supply ? easy memory expansion with ce\ and oe\ options ? all inputs and outputs are ttl-compatible ? three state outputs ? operating temperature range: ceramic -55 o c to +125 o c & -40 o c to +85 o c plastic -40 o c to +85 o c 3 1. not applicable to plastic package 2. applies to cw package only. 3. contact factory for -55 o c to +125 o c options marking ? timing 55ns access -55 4 70ns access -70 85ns access -85 100ns access -100 ? packages ceramic dip (600 mil) cw no. 112 ceramic soj 5 ecj no. 502 plastic tsop dg no. 1002 pin assignment (top view) 32-pin dip, 32-pin soj & 32-pin tsop 4. for dg package, contact factory 5. contact factory note: not all combinations of operating temperature, speed, data retention and low power are necessarily available. please contact the factory for availability of specific part number combinations. 512k x 8 sram ultra low power sram for more products and information please visit our web site at www.austinsemiconductor.com general description the as5c4009ll is organized as 524,288 x 8 sram utilizing a special ultra low power design process. asis pinout adheres to the jedec standard for pinout on 4 megabit srams. the evolutionary 32 pin version allows for easy upgrades from the 1 meg sram design. for flexibility in memory applications, asi offers chip enable (ce\) and output enable (oe\) capabilities. these features can place the outputs in high-z for additional flexibility in system design. this devices operates from a single +5v power supply and all inputs and outputs are fully ttl-compatible. writing to these devices is accomplished when write enable (we\) and ce\ inputs are both low. reading is accomplished when we\ remains high and ce\ and oe\ go low. the device offers a re- duced power standby mode when disabled, by lowering vcc to 2v and maintaining ce\ = 2v. this allows system designers to meet ultra low standby power requirements. pin name function we\ write enable input ce\ chip select input oe\ output enable input a0 - a18 address inputs i/o1 - i/o8 data inputs/outputs vcc power vss ground a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/01 i/02 i/03 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 a17 we\ a13 a8 a9 a11 oe\ a10 ce\ i/08 i/07 i/06 i/05 i/04
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram clk. gen. precharge circuit memory array 1024 rows 512 x 8 columns row select i/o circuit control logic ce\ we\ oe\ i/o 1 i/o 8 a18 a16 a14 a12 a7 a6 a4 a1 a0 a5 column select data cont data cont a9 a8 a13 a17 a15 a10 a11 a3 a2
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings* voltage on vcc supply relative to vss...................-.5v to +7.0v voltage on any pin relative to vss..........................-.5v to +7.0v storage temperature ....................................-65 c to +150 c operating temperature range.............................-55 o c to +125 o c soldering temperature range...............................................260 o c maximum junction temperature**....................................+150 c power dissipation...................................................................1.0w *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ** junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. electrical characteristics and recommended dc operating conditions (-55 o c < t a < 125 o c; vcc = 5v +10%) parameter/condition min max units notes input leakage current (v in = v ss to v cc ) -5 5 ma output leakage current (ce\=v ih or oe\=v ih or we\=v il , v io =v ss to v cc ) -5 5 ma output low voltage (i ol = 2.1ma) -- 0.4 v 15 output high voltage (i oh = -1.0 ma) 2.4 -- v 15 supply voltage 4.5 5.5 v 15 input high (logic 1) voltage 2.2 vcc +0.5 v 1, 15 input low (logic 0) voltage -0.5 0.8 v 2, 15 v il symbol i li i lo v ol v oh v cc v ih conditions sym -55 -70 -85 -100 units notes cycle time = min., 100% duty cycle, i io = 0ma, ce\ = v il , v in = v ih or v il i cc1 100 90 80 70 ma 3 ttl ce\ = v ih , other inputs = v il or v ih i sb 6666ma cmos ce\ = vcc -0.2v, other inputs = 0 ~ vcc i sb1 0.75 0.75 0.75 0.75 ma max power supply current: operating parameter power supply current: standby
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 electrical characteristics and recommended ac operating conditions (-55 o c < t a < 125 o c; vcc = 5v +10%) capacitance parameter symbol maximum units notes input capacitance v in =0v c in 8pf 4 input/output capactiance v io =0v c io 10 pf 4 t a = 25 o c, f = 1mhz v cc = 5v conditions sym min max min max min max min max units notes read cycle read cycle time t rc 55 70 85 100 ns address access time t aa 55 70 85 100 ns chip enable access time t ace 55 70 85 100 ns output hold from address change t oh 10 10 10 10 ns chip enable to output in low-z t lzce 10 10 10 10 ns 4,6 chip disable to output in high-z t hzce 20 25 30 30 ns 4,6 chip enable to power-up time t pu 0000ns4 chip disable to power-down time t pd 55 70 85 100 ns 4 output enable access time t aoe 30 35 40 45 ns output enable to output in low-z t lzoe 5555ns4,6 output disable to output in high-z t hzoe 20 25 30 30 ns 4,6 write cycle write cycle time t wc 55 70 85 100 ns chip enable to end of write t cw 50 60 70 80 ns address valid to end of write t aw 50 60 70 80 ns address setup time t as 0000ns address hold from end of write t ah 0000ns write pulse width t wp1 50 60 70 80 ns data setup time t ds 30 30 35 40 ns data hold time t dh 0000ns write disable to output in low-z t lzwe 5555ns4,6 write enable to output in high-z t hzwe 25 25 30 30 ns 4,6 -100 description -55 -70 -85
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ac test conditions input pulse levels ................................... vss to 3.0v input rise and fall times ....................................... 3ns input timing reference levels ............................. 1.5v output reference levels ..................................... 1.5v output load ......................................... see figures 1 notes 1. overshoot: vcc +3.0v for pulse width < 20ms. 2. undershoot: -3v for pulse width < 20ms. 3. i cc is dependent on output loading and cycle rates. 4. this parameter is guaranteed but not tested. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe . 7. we\ is high for read cycle. 8. device is continuously selected. chip enables and output enables are held in their active state. 9. address valid prior to, or coincident with, latest occurring chip enable. 10. t rc = read cycle time. 11. chip enable and write enable can initiate and terminate a write cycle. 12. output enable (oe\) is inactive (high). 13. output enable (oe\) is active (low). 14. asi does not warrant functionality nor reliability of any product in which the junction temperature exceeds 150c. care should be taken to limit power to acceptable levels. 15. all voltage referenced to vss (gnd). fig. 1 output load equivalent data retention electrical characteristics description symbol min max units notes v cc for retention data v dr 2v ce\ > (v cc - 0.2v) v cc = 2v i ccdr 100 m a v in > (v cc - 0.2v) v cc = 3v i ccdr 200 m a chip deselect to data retention time t cdr 0ns4 operation recovery time t r 5 ms 4, 10 data retention current conditions 167 ohms 1.73v c=30pf q c = 100pf 50 ohms
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 read cycle no. 1 1 (address controlled, ce\ = oe\ = v il , we\ = v ih ) read cycle no. 2 2 (we\ = v ih ) low v cc data retention waveform address t rc 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 12345678901 1 234567890 1 1 234567890 1 1 234567890 1 1 234567890 1 12345678901 12 12 12 12 12 12 12 12 12 12 12 12 t oh t aa previous data valid data valid data out address t rc t aa ce\ 123456 123456 123456 123456 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 123456 123456 123456 123456 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 t co1 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 123456789 123456789 123456789 123456789 123456789 12345678901234567890 1 234567890123456789 0 1 234567890123456789 0 1 234567890123456789 0 12345678901234567890 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 t oe 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234 123 4 123 4 123 4 123 4 1234 12 12 12 12 12 12 12 12 12 12 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234567 1234 1 23 4 1 23 4 1 23 4 1 23 4 1234 1 1 1 1 1 12 12 12 12 12 data valid high-z t oh t hz t ohz t olz t lz oe\ data out 12345 1 234 5 1 234 5 1 234 5 12345 dont care undefined 12345 1 234 5 1 234 5 1 234 5 1 234 5 12345 t sdr t rdr data retention v cc 4.5v 2.2v v dr gnd ce\ ce\ > vcc - 0.2v ce\ controlled
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 write cycle no. 1 (we controlled) write cycle no. 2 (write enabled controlled) notes: 1. thz and tohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature adn voltage condition, thz (max) is less than tlz (min) both for a given d evice and from device to device interconnection. 3. a write occurs during the overlap of a low ce\ adn a low we\. a write begins at the latest transistion among ce\ going low and we\ going low: a write end at the earliest transistion among ce\ going high and we\ going high, twp is measured from the beginning of write to the end of write. 4. tcw is measured from the ce\ going low to end of write. 5. tas is measured from the address valid to the beginning of write. 6. twr is measure from the end of write to the address change. twr applied in case a write ends are ce\ or we\ going high. address t wc t cw(4) ce\ 123456789 123456789 123456789 123456789 123456789 123456789012345678901 1 2345678901234567890 1 1 2345678901234567890 1 1 2345678901234567890 1 123456789012345678901 1234567890123456789012 1 23456789012345678901 2 1 23456789012345678901 2 1234567890123456789012 123456 123456 123456 123456 123456 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 12345678901234567 1 234567890123456 7 1 234567890123456 7 12345678901234567 t aw data valid t wr(6) t as(5) data out 1234567 1234567 1234567 1234567 1234567 data undefined t wp(3) t dw t dh t whz t ow we\ data in 123456789 123456789 123456789 123456789 1234567890123456789012345 1 23456789012345678901234 5 1 23456789012345678901234 5 1234567890123456789012345 12345678901234567890123456 1 234567890123456789012345 6 1 234567890123456789012345 6 12345678901234567890123456 1234567 1234567 1234567 1234567 123456789012345678 1 2345678901234567 8 1 2345678901234567 8 123456789012345678 123456789012345678 1 2345678901234567 8 1 2345678901234567 8 123456789012345678 address t wc t cw(4) ce\ t aw data valid t wr(6) t as(5) data out t wp(3) t dw t dh we\ data in high-z high-z
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 asi case #112 (package designator cw) e b b1 l l1 a mechanical definition* d pin 1 e e1 b2 min max a 0.089 0.111 b 0.016 0.020 b1 0.045 0.055 b2 0.008 0.012 d 1.585 1.615 e 0.585 0.605 e1 0.590 0.610 e 0.090 0.110 l 0.040 0.060 l1 0.125 0.175 symbol asi package *all measurements are in inches.
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 asi case #502 (package designator ecj) mechanical definition* *all measurements are in inches. l e1 a a1 e b d e d1 b2 b1

sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 asi case #1002 (package designator dg) mechanical definition* *all measurements are in inches. 0.4630.008 0.400 typ 0 - 8 0.006 +0.004/-0.002 0.018 ~ 0.030 0.050 typ 0.016 0.004 0.037 typ 0.841 max 0.825 0.004 0.002 min 0.039 0.004 0.047 max 0.004 max
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 ordering information *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c **note: all csoj devices, please consult factory. not all combinations of operating temperature, speed, data retention and low power are necessarily available. please contact the factory for availability of specific part number combinations. *** note: plastic devices not available as 883. for xt or 55ns devices, contact factory. device number package type speed ns process device number package type speed ns process as5c4009ll cw -55 /* as5c4009ll ecj -55 /* as5c4009ll cw -70 /* as5c4009ll ecj -70 /* as5c4009ll cw -85 /* as5c4009ll ecj -85 /* as5c4009ll cw -100 /* as5c4009ll ecj -100 /* device number package type speed ns process as5c4009ll dg -55 /* as5c4009ll dg -70 /* as5c4009ll dg -85 /* as5c4009ll dg -100 /* example: as5c4009lldg-55/it *** example: as5c4009llecj-55/883c ** example: as5c4009llcw-55/883c **
sram as5c4009ll austin semiconductor, inc. as5c4009ll rev. 4.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 asi to dscc part number cross reference for 5962-95613 * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd. package designator cw asi part # smd part as5c4009cw-120/h 5962-9561301hya as5c4009cw-120l/h 5962-9561315hya as5c4009cw-100/h 5962-9561302hya as5c4009cw-100l/h 5962-9561316hya as5c4009cw-85/h 5962-9561303hya as5c4009cw-85l/h 5962-9561317hya as5c4009cw-70/h 5962-9561304hya as5c4009cw-70l/h 5962-9561318hya as5c4009cw-120/h 5962-9561301hyc as5c4009cw-120l/h 5962-9561315hyc as5c4009cw-100/h 5962-9561302hyc as5c4009cw-100l/h 5962-9561316hyc as5c4009cw-85/h 5962-9561303hyc as5c4009cw-85l/h 5962-9561317hyc as5c4009cw-70/h 5962-9561304hyc as5c4009cw-70l/h 5962-9561318hyc

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